AD9084

预发布

Apollo MxFE Quad, 16-Bit, 28 GSPS RF DAC and Quad, 12-Bit, 20 GSPS RF ADC

数据手册 (Rev. PrA) 产品选型表
产品技术资料帮助

ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许，也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。
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  • 产品详情
  • 参考资料
  • 硬件生态系统
  • 工具及仿真模型
  • 评估套件
  • 最新评论
    •

    产品详情

    • Flexible reconfigurable common platform design
      • 4 DACs and 4 ADCs (4D4A)
      • Usable RF Analog bandwidth up to 18 GHz
      • Maximum DAC/ADC sample rate up to 28 GSPS/20 GSPS
    • DAC to ADC sample rate ratios of 1 and 2
      • Clocking
      • On-chip PLL (7 GHz to 14 GHz)
    • External RFCLK input up to 20 GHz
    • Multichip synchronization via subclass1
    • Single-ended (SE) or differential (DIFF) ADC inputs
      • Two separate versions, both 50 Ω input impedance
      • Single-ended version with on-chip wide bandwidth balun
    • Differential ADC AC performance at 20 GSPS
      • Full-scale input voltage: 500 mV p-p/−2 dBm
      • Noise density: −150 dBFS/Hz at −20 dBFS at 2 GHz
      • HD2/HD3: −65 dBFS/−70 dBFS at −7 dBFS at 2 GHz
      • IMD3: −75 dBFS at – 13 dBFS/tone at 2 GHz
    • DAC AC performance at 28 GSPS
      • Full-scale output power: −2.1 dBm at 2 GHz
      • IMD3: −75 dBc at – 13 dBFS/tone at 2 GHz to 10 GHz
      • NSD (shuffling disabled): −164 dBFS/Hz at 0 dBFS at 2 GHz
    • Versatile digital features
      • Supports real or complex digital data (8-, 12-, 16-bit)
      • Configurable DDC and DUC
      • 8 fine complex DUCs and 4 coarse complex DUCs
      • 8 fine complex DDCs and 4 coarse complex DDCs
      • Option to bypass fine and coarse DUC/DDC
      • DUC/DDC alias rejection
      • 85 dB for interpolation filters
      • 100 dB for decimation filters
      • Fractional sample rate converter (FSRC)
    • Programmable FIR filters for transmit/receive
    • Multiple loopback (ADC to DAC) supported
      • ~45 ns without DSP path
    • Dynamic configuration through SPI/HSCI/GPIO
    • Spectrum sniffer/monitor
    • Interfaces
      • SPI
      • High-Speed Control Interface (HSCI)
      • JESD204B/JESD204C: 20 Gbps/32.5 Gbps
    • 24 lanes for Rx, 24 lanes for Tx
    • Receive AGC support
      • Fast detect with low latency for fast AGC control
      • Signal monitor for slow AGC control
    • Auxiliary features
      • Power amplifier downstream protection circuitry
      • On-chip temperature monitoring unit
      • TDD power savings option
    • Total power consumption range dependent on device configuration: 20 W to 30 W
    • 24 mm × 26 mm, 899-ball BGA with 0.8 mm pitch
    • Operating junction temperature (TJ): −40°C to +110°C
    AD9084
    Apollo MxFE Quad, 16-Bit, 28 GSPS RF DAC and Quad, 12-Bit, 20 GSPS RF ADC
    提问

    参考资料

    数据手册 1

    用户手册 1

    技术文章 7

    了解更多

    硬件生态系统

    部分模型 产品周期 描述
    ADF4030
    		预发布 10-Channel Precision Synchronizer
    LDO Linear Regulators 2
    LTM4709
    		推荐新设计使用 具有可配置输出阵列的三通道3A、超低噪声、高PSRR、超快速μModule线性稳压器
    LT3094
    		推荐新设计使用 −20V、500mA、超低噪声、超高 PSRR 负线性稳压器
    RF VGA（可变增益放大器） 2
    ADL6331
    		预发布 0.38 GHz 至 12 GHz TxVGA
    Modal heading
    添加至 myAnalog

    将产品添加到myAnalog 的现有项目或新项目中（接收通知）。

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    工具及仿真模型

    Data Conversion Calculator

    Calculate ENOB, SNR, SINAD, THD.

    打开工具

    Clock & Timing Tools

    Analog Devices provides design tools that work with our product portfolio to help engineers build critical clock and timing IC solutions for wired and wireless networks.

    打开工具

    折频工具

    该工具展示了输入信号及其谐波通过ADC实现数字化时的混叠效应。用户可选择单音或调制载波输入信号，并观察多达10个奈奎斯特区域内的混叠效应。

    打开工具

    SNR/THD/SINAD计算器

    此计算器可将SNR、THD和SINAD转换为ENOB和噪声。 它还能根据SNR、THD或SINAD中的两个参数计算另一个参数。

    打开工具

    评估套件

    eval board
    schematic 1
    schematic 2
    schematic 3
    ADS10-V1EBZ

    ADS10-V1EBZ Evaluation Board

    立即购买 更多内容

    特性和优点

    Xilinx Virtex Ultrascale+ XCVU35P-3FSHV2892E FPGA.

    • One (1) FMC+ connector.
    • Twenty (24) 32.75Gbps transceivers supported by one (1) FMC+ connector.
    • On-board HBM DRAM in FPGA.
    • Simple USB 3.0 port interface.

    产品详情

    When connected to a specified Analog Devices high speed converter evaluation board, the ADS10-V1EBZ works as a data capture/transmit board. Designed to support the highest speed JESD204B/C data converters, the FPGA on the ADS10-V1EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.

    ADS10-V1EBZ
    ADS10-V1EBZ Evaluation Board

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