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HMC438

RECOMMENDED FOR NEW DESIGNS

SMT GaAs HBT MMIC
Divide-by-5, DC - 7 GHz

Data Sheet

Part Models: 4
1ku List Price: price unavailable

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Part Details

SSB Phase Noise: -153 dBc/Hz @100KHz
Wide Bandwidth
Output Power: -1 dBm
Single DC Supply: +5V @ 80 mA
MS8G SMT Package

Part Models: 4
1ku List Price: price unavailable

Documentation

Data Sheet 1

HMC438 Data Sheet 04/22/2015

Application Note 1

AN-1463: Frequency Divider Operation and Compensation with No Input Signal (Rev.A) 06/01/2017

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
HMC438MS8G	8-Lead MSOP w/ EP	Material Declaration Reliablity Data	Ultra Librarian SamacSys
HMC438MS8GE	8-Lead MSOP w/ EP	Material Declaration Reliablity Data	Ultra Librarian SamacSys
HMC438MS8GETR	8-Lead MSOP w/ EP	Material Declaration Reliablity Data	Ultra Librarian SamacSys
HMC438MS8GTR	8-Lead MSOP w/ EP	Material Declaration Reliablity Data	Ultra Librarian SamacSys

Part Models	Product Lifecycle	PCN
No Match Found
May 6, 2019 - 19_0063 Assembly Site Transfer of Select MSOP and SOIC_N E-pad Devices to Carsem Malaysia
		PCN19_0063_Form Material_Report Other Qualification Results Summary Qualification Results Summary Other
HMC438MS8G	PRODUCTION
HMC438MS8GE	PRODUCTION
HMC438MS8GETR	PRODUCTION
HMC438MS8GTR	PRODUCTION

This is the most up-to-date revision of the Data Sheet.

Tools & Simulations

ADIsimPLL™

ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.

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