AD6672

RECOMMENDED FOR NEW DESIGNS

IF Receiver

Data Sheet (Rev. C)

Part Models: 2
1ku List Price: Starting From $56.75

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Part Details

11-bit, 250MSPS output data rate
Performance with NSR enabled
SNR: 75.2 dBFS in a 55 MHz band to 185 MHz at 250 MSPS
SNR: 72.8 dBFS in an 82 MHz band to 185 MHz at 250 MSPS
Performance with NSR disabled
SNR: 66.4 dBFS up to 185 MHz at 250 MSPS
SFDR: 87 dBc up to 185 MHz at 250 MSPS
Total power consumption: 358 mW at 250 MSPS
1.8 V supply voltages

LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Internal ADC voltage reference
Flexible analog input range
1.4 V_p-p to 2.0 V_p-p
(1.75 V p-p nominal)
Differential analog inputs with 350 MHz bandwidth
Serial port control
Energy saving power-down modes
User-configurable, built-in self test (BIST) capability

Part Models: 2
1ku List Price: Starting From $56.75

Documentation

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
AD6672BCPZ-250	32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD6672BCPZRL7-250	32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)	Material Declaration Reliablity Data	Ultra Librarian SamacSys

This is the most up-to-date revision of the Data Sheet.

Software Resources

Evaluation Software 1

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

JESD204x Frame Mapping Table Generator

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Hardware Ecosystem

Parts	Product Life Cycle	Description
AD9511	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
Clocks 7
AD9512	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs
AD9513	RECOMMENDED FOR NEW DESIGNS	800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9514	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

AD9515	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
AD9523	NOT RECOMMENDED FOR NEW DESIGNS	14-Output, Low Jitter Clock generator
AD9523-1	RECOMMENDED FOR NEW DESIGNS	Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
AD9524	NOT RECOMMENDED FOR NEW DESIGNS	6 Output, Dual Loop Clock Generator
Differential Amplifiers 3
ADA4927-1	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion Current Feedback Differential ADC Driver
ADA4938-1	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion Differential ADC Driver (Single)
ADL5562	RECOMMENDED FOR NEW DESIGNS	3.3 GHz Ultralow Distortion RF/IF Differential Amplifier
PLL Synthesizers 1
AD9510	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
Variable Gain Amplifiers 2
ADL5202	Obsolete	Wide Dynamic Range, High Speed, Digitally Controlled VGA
AD8376	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion IF Dual VGA

Tools & Simulations

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

Open Tool

ADC Companion Transport Layer RTL Code Generator Tool

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

Open Tool

Visual Analog

For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.

Open Tool

AD6672 IBIS Model 1

AD6672BCPZ (All Speed Grades)

S-Parameter 1

AD6672 Analog Input S-Parameter

Evaluation Kits

AD9642 Evaluation Board

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Features and Benefits

Full featured evaluation board for the AD9642/AD9634/AD6672
SPI interface for setup and control
External or AD9523 clocking option
Balun/transformer or amplifier input drive option
LDO regulator power supply
VisualAnalog and SPI controller software interfaces

Product Details

The AD9642, AD9634, and AD6672 evaluation board, which provides all of the support circuitry required to operate the AD9642, AD9634, and AD6672 in their various modes and configurations. The application software used to interface with the devices is also described.

The AD9642, AD9634, and AD6672 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at http://www.analog.com/fifo. For additional information or questions, send an email to highspeed.converters@analog.com.

Resources

UG-386: Evaluating the AD9642/AD9634/AD6672 Analog-to-Digital Converters
4/12/2012

AD9642/AD9634/AD6672 Evaluation Board Schematic
8/17/2011

AD9642 Quick Start Guide
8/10/2011

FPGA-Based Data Capture Kit

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Features and Benefits

64kB FIFO Depth
Works with single and multi-channel ADCs
Use with VisualAnalog^® software
Based on Virtex-4 FPGA
May require adaptor to interface with some ADC eval boards
Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
DDR Encode Rates on each channel

Product Details

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog^® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.