AD6657A
RECOMMENDED FOR NEW DESIGNS65MHz Bandwidth Quad IF Receiver
- Part Models
- 2
- 1ku List Price
- Starting From $142.97
Part Details
- 11-bit, 200 MSPS output data rate per channel
- Performance with NSR enabled
- SNR: 75.5 dBFS in 40 MHz band to 70 MHz at 185 MSPS
- SNR: 73.7 dBFS in 60 MHz band to 70 MHz at 185 MSPS
- SNR: 70.0 dBFS in 65 MHz band to 70 MHz at 185 MSPS - Performance with NSR disabled
- SNR: 66.5 dBFS to 70 MHz at 185 MSPS
- SFDR: 89 dBc to 70 MHz at 185 MSPS
- Integrated noise shaping requantizer
- Low power: 1.2 W at 185 MSPS
- 1.8 V analog supply operation
- 1.8 V LVDS (ANSI-644 levels) output
- 1-to-8 integer clock divider
- Internal ADC voltage reference
- 1.75 V p-p analog input range (programmable to 2.0 Vp-p)
- See data sheet for additional features
The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate frequency (IF) receiver specifically designed to support multiple antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.
The device consists of four high performance ADCs and NSR digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI.
With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6657A supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22%, 33%, or 36% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6657A can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode, up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode, or up to 70.0 dBFS SNR for a 65 MHz bandwidth in the 36% mode.
With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6657A can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6657A to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are used.
After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels. The AD6657A receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.
Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board level system testing.
The AD6657A is available in a Pb-free, RoHS-compliant, 144 ball, 10 mm × 10 mm chip scale package ball grid array (CSP_BGA) that is specified over the industrial temperature range of −40°C to +85°C.
APPLICATIONS
- Communications
- Diversity radio and smart antenna (MIMO) systems
- Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA - I/Q demodulation systems
- General-purpose software radios
PRODUCT HIGHLIGHTS
- Four analog-to-digital converters (ADCs) are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.
- Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 65 MHz at 185 MSPS.
- LVDS digital output interface configured for low cost FPGA families.
- 230 mW per ADC core power consumption. 5. Operation from a single 1.8 V supply.
- Standard SPI that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode.
- On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.
Documentation
Data Sheet 1
User Guide 1
Application Note 10
Evaluation Design File 1
Circuit Note 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD6657ABBCZ | 144-Ball CSPBGA (10mm x 10mm x 1.4mm) | ||
| AD6657ABBCZRL | 144-Ball CSPBGA (10mm x 10mm x 1.4mm) |
This is the most up-to-date revision of the Data Sheet.
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Open ToolAD6657A IBIS Model 1
Evaluation Kits
AD6657A Evaluation Board
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