MAX12558
Dual, 80Msps, 14-Bit, IF/Baseband ADC
Ideal for High-Performance Communication Receivers
Part Details
- Direct IF Sampling Up to 400MHz
- Excellent Dynamic Performance
- 74.4dB/71.7dB SNR at fIN = 70MHz/175MHz
- 84.2dBc/79dBc SFDR at fIN = 70MHz/175MHz
- 3.3V Low-Power Operation
- 789mW (Differential Clock Mode)
- 756mW (Single-Ended Clock Mode)
- Fully Differential or Single-Ended Analog Input
- Adjustable Differential Analog Input Voltage
- 750MHz Input Bandwidth
- Adjustable, Internal or External, Shared Reference
- Differential or Single-Ended Clock
- Accepts 25% to 75% Clock Duty Cycle
- User-Selectable DIV2 and DIV4 Clock Modes
- Power-Down Mode
- CMOS Outputs in Two's Complement or Gray Code
- Out-of-Range and Data-Valid Indicators
- Small, 68-Pin Thin QFN Package (10mm x 10mm x 0.8mm)
- 12-Bit, Pin-Compatible Version Available (MAX12528)
- Evaluation Kit Available (Order MAX12558EVKIT)
The MAX12558 is a dual 3.3V, 14-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving internal quantizers. The MAX12558 is optimized for low power, small size, and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual ADC operates from a single 3.3V supply, consuming only 756mW while delivering a typical 71.7dB signal-tonoise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or differential inputs up to 400MHz. In addition to low operating power, the MAX12558 features a 330µW powerdown mode to conserve power during idle periods.
A flexible reference structure allows the MAX12558 to use the internal 2.048V bandgap reference or accept an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX12558 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits.
The MAX12558 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2) and divide-by-four (DIV4) modes allow for design flexibility and help to reduce the negative effects of clock jitter. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer (DCE).
The MAX12558 features two parallel, 14-bit-wide, CMOS-compatible outputs. The digital output format is pin-selectable to be either two's complement or Gray code. A separate power-supply input for the digital outputs accepts a 1.7V to 3.6V voltage for flexible interfacing with various logic levels. The MAX12558 is available in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package with exposed paddle (EP), and is specified for the extended (-40°C to +85°C) temperature range.
Applications
- Digital Set-Top Boxes
- I/Q Receivers
- IF and Baseband Communication Receivers: Cellular, LMDS, Point-to-Point Microwave, MMDS, HFC, WLAN
- Low-Power Data Acquisition
- Portable Instrumentation
- Ultrasound and Medical Imaging
Documentation
Data Sheet 1
Design Note 2
Technical Articles 2
This is the most up-to-date revision of the Data Sheet.
Software Resources
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| Parts | Product Life Cycle | Description |
|---|---|---|
| Analog to Digital Converters 5 | ||
| MAX12527 | PRODUCTION | Dual, 65Msps, 12-Bit, IF/Baseband ADC |
| MAX12528 | Dual, 80Msps, 12-Bit, IF/Baseband ADC | |
| MAX12557 | PRODUCTION | Dual, 65Msps, 14-Bit, IF/Baseband ADC |
| MAX12559 | Dual, 96Msps, 14-Bit, IF/Baseband ADC | |
| MAX12529 | Dual, 96Msps, 12-Bit, IF/Baseband ADC |
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