ADSP-2181
NOT RECOMMENDED FOR NEW DESIGNS16-bit, 40 MIPS, 5v, 2 Serial Ports, Host Port, 80 KB RAM
Part Details
- 25 ns Instruction Cycle Time from 20 MHz Crystal @ 5.0 Volts
- 40 MIPS Sustained Performance
- ADSP-2100 Family Code Compatible, with Instruction Set Extensions
- 80K Bytes of On-Chip RAM, Configured as 16K Words On-Chip Program Memory RAM and 16K Words On-Chip Data Memory RAM
- Dual Purpose Program Memory for Both Instruction and Data Storage
- 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory
- 4 MByte Memory Interface for Storage of Data Tables and Program Overlays
- 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers
The ADSP-2181 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.
The ADSP-2181 combines the ADSP-2100 family base architecture(three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory.
The ADSP-2181 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2181 is available in 128-pin TQFP and 128- pin PQFP packages.
In addition, the ADSP-2181 supports new instructions, which include bit manipulations-bit set, bit clear, bit toggle, bit test- new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2181 operates with a 30 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2181's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2181 can:
- Generate the next program address
- Fetch the next instruction
- Perform one or two data moves
- Update one or two data address pointers
- Perform a computational operation
Documentation
Data Sheet 1
User Guide 1
Application Note 71
Technical Articles 1
Processor Manual 4
Software Manual 4
Integrated Circuit Anomaly 1
Legacy Emulator Manual 1
This is the most up-to-date revision of the Data Sheet.
Software Resources
Code Examples 1
Software & Tools Anomaly 1
Evaluation Software 0
Tools & Simulations
ADSP-21xx Processors: Software and Tools
Open Tool
Evaluation Kits
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