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ADRV9008-2
RECOMMENDED FOR NEW DESIGNSIntegrated Dual RF Transmitter and Observation Receiver
- Part Models
- 2
- 1ku List Price
- Starting From $306.88
Part Details
- Dual transmitters
- Dual input shared observation Rx
- Maximum tunable Tx synthesis BW: 450 MHz
- Maximum observation Rx BW: 450 MHz
- Fully integrated fractional-N RF synthesizers
- Fully integrated clock synthesizer
- Multi-chip phase synchronization for RF LO and baseband clocks
- JESD204B datapath interface
- Tuning range: 75 MHz to 6000 MHz
The ADRV9008-2 is a highly integrated, RF agile transmit subsystem offering dual channel transmitters, observation path receiver, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 2G, 3G and 4G macro-cell base stations, and active antenna, applications.
The transmitters use an innovative direct conversion modulator that achieves multi-carrier macro-base-station quality performance and very low power. In 3G/4G mode, the maximum large-signal bandwidth is 200MHz. In MC-GSM mode, which has higher in-band SFDR, the maximum large-signal bandwidth is 75MHz.
The observation path consists of a wide bandwidth direct-conversion receiver with state-of-the-art dynamic range. The complete receive subsystem includes dc offset correction, quadrature correction, and digital filtering thus eliminating the need for these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-front-end control are also integrated.
The fully integrated phase locked loops (PLLs) provide high performance, low power fractional-N RF frequency synthesis for the transmitter and receiver sections. An additional synthesizer is used to generate the clocks needed for the converters, digital circuits, and the serial interface. Special precautions have been taken to provide the isolation demanded in high performance base station applications. All VCO and loop filter components are integrated.
The high-speed JESD204B interface supports up to 12.288 Gbps lane rates resulting in two lanes per transmitter in the widest bandwidth mode and two lanes for the observation path receiver in the widest bandwidth mode.
The core of the ADRV9008-2 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4 wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9008-2 is packaged in a 12mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
Documentation
Data Sheet 1
User Guide 1
Technical Articles 1
Video 1
Device Drivers 1
Solutions Bulletin & Brochure 1
Product Selection Guide 1
Webcast 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| ADRV9008BBCZ-2 | 196-Ball CSPBGA (12mm x 12mm) | ||
| ADRV9008BBCZ-2REEL | 196-Ball CSPBGA (12mm x 12mm) |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 1
Wideband RF Transceiver Evaluation Software
The Evaluation kit offers several software drivers for evaluation and rapid prototyping as well as design tool options to aid in simulation and filter design.
Evaluation Kits
ADRV9008/ADRV9009 Evaluation Board
Resources
Software
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