AD7725

Obsolete

16-Bit Sigma Delta ADC with a Programmable Post Processor

Data Sheet (Rev. A)

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Part Details

Programmable Filtering
- Any Characteristic up to 108 Tap FIR and/or IIR
Polynomial Signal Conditioning up to 8^th Order
Flexible Programming Modes
- Boot from DSP or External EPROM
- Parallel/Serial Interface
Internal Default Filter for Evaluation
Programmable Decimation and Output Word Rate

14.4 MHz Max Master Clock Frequency
0 V to +4 V (Single-Ended) or ±2 V (Differential) Input Range
Power Supplies: AV_DD, DV_DD: 5 V ± 5%
On-Chip 2.5 V Voltage Reference
44-Lead MQFP Package

Documentation

Data Sheet 1

AD7725: 16-Bit 900 kSPS Sigma-Delta ADC with Programmable Post Processor Data Sheet (Rev.A) 01/13/2003

Application Note 7

AN-342: Analog Signal-Handling for High Speed and Accuracy 02/14/2015

AN-311: How to Reliably Protect CMOS Circuits Against Power Supply Overvoltaging 03/08/2008

AN-280: Mixed Signal Circuit Technologies 02/14/2015

AN-282: Fundamentals of Sampled Data Systems 02/14/2015

AN-283: Sigma-Delta ADCs and DACs 09/24/2002

AN-388: Using Sigma-Delta Converters-Part 1 02/14/2015

AN-389: Using Sigma-Delta Converters-Part 2 02/14/2015

Technical Articles 2

Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter 01/12/2006

Designing Power Supplies for High Speed ADC 02/01/2012

This is the most up-to-date revision of the Data Sheet.

Software Resources

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Tools & Simulations

Sigma-Delta ADC Tutorial

An interactive illustration showing the behavior of an idealized sigma-delta A/D converter.

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