ADP5014

RECOMMENDED FOR NEW DESIGNS

Integrated Power Solution with Quad Low Noise Buck Regulators

Part Models
1
1ku List Price
Starting From $3.52

Part Details

  • Input voltage range: 2.75 V to 6.0 V
  • Programmable output voltage range: 0.5 V to 0.9 × PVINx
  • Low output noise: ~25 μV rms when VOUT ≤ VREF
  • ±1.0% output accuracy over full temperature range
  • 500 kHz to 2.5 MHz adjustable switching frequency
  • Power regulation
    • Channel 1 and Channel 2: programmable 2 A/4 A sync buck regulators, or single 8 A output in parallel
    • Channel 3 and Channel 4: programmable 1 A/2 A sync buck regulators, or single 4 A output in parallel
  • Flexible parallel operation
  • Precision enable with 0.6 V threshold
  • Manual or sequence mode for power-up and power-down sequence
  • Selective FPWM or PSM operation mode
  • Precision undervoltage comparator
  • Frequency synchronization input or output
  • Active output discharge switch
  • Power-good flag on selective channels via factory fuse
  • UVLO, OVP, OCP, and TSD protection
  • 40-lead, 6 mm × 6 mm LFCSP package
  • −40°C to +125°C junction temperature
ADP5014

Integrated Power Solution with Quad Low Noise Buck Regulators

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Documentation

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Tools & Simulations

LTspice


Models for the following parts are available in LTspice:

  • ADP5014
LTspice

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.


Reference Designs

Artix US+ Rail Consolidation – Minimum Rails (AU10P/15P) Power Tree
Artix UltraScale+ Circuits from the lab

Minimum Rails for AU10/15P and AU20/25P - Non-Hardware Verified Design

Features and Benefits

  • Xilinx Artix® UltraScale+ devices are the industry’s only cost-optimized FPGAs based on an advanced, production-proven 16nm architecture for best-in-class performance/watt.

  • Analog Devices, Inc. supports power delivery solutions for the Artix Ultrascale+ low-cost designs. Monolithic solutions are used to power Xilinx FPGA and/or SoC rails as well as other system rails. These regulators are highly integrated discrete solutions optimized for cost, efficiency and footprint.

  • ADI provides supporting documentation including power schematics, layout, LTpowerPlanner® and applicable LTpowerPlay® configuration files to enable you to validate the power solution for your application seamlessly.

  • For a complete list power designs and use cases, please contact your local FAE.

  • Key Power for full management devices are used as follows:

    • LTC3307A
    • LTC3309A
    • ADP125
    • LTC3617 (Optional DDR)
    • LTC3618
    • ADM1186 (Optional Monitoring & Sequencing)
Artix UltraScale+
Minimum Rails for AU10/15P and AU20/25P - Non-Hardware Verified Design

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