SPI Library Description


The SPI Library is a C interface library that may be used on the DS80C400. It provides a simple interface to allow communication with SPI devices using Port 5's PCEN pins. The library has the following features:

  • Four SPI Clock Modes
  • 8 and 16 Bit Word Transfers
  • SPI Clock Stretching
  • Multiple Slave Select Modes
  • Optional Atomic Transfers
  • Optional bit Reversal


  • The four SPI clock (SPI_CLK) modes supported by this library are defined by CKPHA and CKPOL. The CKPOL bit defines the idle state of the SPI clock, CKPOL = 0 forces SPI_CLK to idle low while CKPOL = 1 forces SPI_CLK to idle high. CKPHA changes the edge used to signal transfer of data. When CKPHA = 0 the first edge of SPI_CLK specifies when the slave and master should sample their input. With CKPHA = 1 the second edge of SPI_CLK specifies when to sample. When CKPHA = 1, the master and slave should present their data on their output during the first SPI_CLK edge, this allows the data sufficent hold time. When CKPHA = 0, data should become valid when the Slave Select (SS) line goes active. Note that most devices require the SS line to be used when CKPHA = 0 to allow proper timing while SS may be optional when CKPHA = 1. Figure 2 illistrates this behaviour.

    Data is sent to the SPI library as a byte array in data memory. When in 8 bit word mode these bytes will be transferred one at a time. In 16 bit word mode 2 bytes will be transferred but this operation will only consume 1 transfer of the number requested. Note that in this document, "word" may be 8 or 16 bits in length depending on the selected mode.

    In order to interface to slower SPI slaves a SPI_CLK stretch can be used to increases the SPI_CLK period by 1 µsec per stretch.

    The SS signal is optional as it may not be required for all SPI setups. Most SPI devices expect the active state for SS to be low, but others require high as the active state. Some SPI devices expect the SS signal to go inactive after each word transfer in order to synchronize.

    To facilitate atomic transfers interrupts may be disabled while transmiting.

    If desired the bit order of the data can be modifed so that bits are transmitted LSB first instead of MSB.


    SPI Library Sample Applications

    The SPI sample application utilizes the library to control a MAX1080 ADC.




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