-- ********************************************************* -- BSDL file for design ad6634 -- Created by Synopsys Version 1999.05 (Dec 18, 1998) -- Revised : Kasyap Yadavelli (4/17/2003) -- Designer: Satya Nayak -- Company: Analog Devices -- Date: Fri Jun 14 09:42:16 2002 -- ********************************************************** entity ad6634 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "AD6634"); -- This section declares all the ports in the design. port ( INB2 : in bit; INB3 : in bit; INB0 : in bit; INB1 : in bit; IENB : in bit; LIB_B : out bit; CLK : in bit; INA13 : in bit; INA12 : in bit; EXPA0 : in bit; INA11 : in bit; INA10 : in bit; INA8 : in bit; EXPA1 : in bit; INA9 : in bit; INA6 : in bit; EXPA2 : in bit; INA7 : in bit; INA4 : in bit; INA5 : in bit; INA2 : in bit; INA0 : in bit; INA3 : in bit; IENA : in bit; INA1 : in bit; LIB_A : out bit; LIA_B : out bit; LIA_A : out bit; SYNCB : in bit; SYNCA : in bit; DTACK : out bit; SYNCD : in bit; SYNCC : in bit; MODE : in bit; RESET : in bit; D7 : inout bit; D6 : inout bit; CS : in bit; D5 : inout bit; D4 : inout bit; D2 : inout bit; R_W : in bit; D3 : inout bit; D0 : inout bit; TRST : in bit; D1 : inout bit; SBM0_PA6_LA6 : inout bit; DS : in bit; A0 : in bit; A2 : in bit; --50 PACH0_LACLKOUT: out bit; A1 : in bit; SDIV02_PA7_LA7: inout bit; PACH1_LACLKIN : inout bit; PA4_LA4 : out bit; SDIV03_PA5_LA5: inout bit; PA3_LA3 : out bit; PA2_LA2 : out bit; PA1_LA1 : out bit; SDIV00_PA8 : inout bit; PA0_LA0 : out bit; TCLK : in bit; SDFS0_PA10 : inout bit; SDIV01_PA9 : inout bit; TDO : out bit; SDO0_PA11 : out bit; SDFE0_PA12 : out bit; SCLK1_PA13 : inout bit; SDR0_PAREQ : out bit; PA14 : out bit; TMS : in bit; TDI : in bit; CHIP_ID1 : in bit; CHIP_ID0 : in bit; CHIP_ID3 : in bit; SDR1_PAACK : in bit; CHIP_ID2 : in bit; SDIN1_PAIQ : inout bit; SCLK0 : inout bit; PB6_LB6 : out bit; SDIN0 : in bit; PBIQ : out bit; SDIN2_PB7_LB7 : inout bit; SDFE1_PCLK : inout bit; PBCH0_LBCLKOUT: out bit; SCLK2_PB3_LB3 : inout bit; PBCH1_LBCLKIN : inout bit; PB0_LB0 : out bit; PB5_LB5 : out bit; PB4_LB4 : out bit; SDFS1_PB2_LB2 : inout bit; SDO1_PA15 : out bit; SDO2_PB8 : out bit; SDFS2_PB1_LB1 : inout bit; SDFE2_PB11 : out bit; SCLK3_PB10 : inout bit; PB9 : out bit; SDFE3_PB13 : out bit; SDFS3_PB12 : inout bit; SDO3_PB14 : out bit; --100 SDR2_PBREQ : out bit; SDIN3_PB15 : inout bit; INB13 : in bit; SDR3_PBACK : in bit; INB12 : in bit; INB11 : in bit; PL_SER : in bit; -- should always be tied to VDDIO EXPB1 : in bit; INB10 : in bit; INB9 : in bit; EXPB0 : in bit; INB7 : in bit; INB8 : in bit; EXPB2 : in bit; INB5 : in bit; INB6 : in bit; INB4 : in bit; --117 VDDRING : linkage bit_vector (1 to 10); VSSRING : linkage bit_vector (1 to 8); VDDCORE : linkage bit_vector (1 to 10); VSSCORE : linkage bit_vector (1 to 8)); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ad6634: entity is "STD_1149_1_1993"; attribute PIN_MAP of ad6634: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant AD6634: PIN_MAP_STRING := "INB2 : B1 ,"& "INB3 : C2 ,"& "INB0 : C1 ,"& "INB1 : D2 ,"& "IENB : E2 ,"& "LIB_B : D1 ,"& "CLK : E1 ,"& "INA13 : G2 ,"& "INA12 : G1 ,"& "EXPA0 : F2 ,"& "INA11 : H1 ,"& "INA10 : G3 ,"& "INA8 : J1 ,"& "EXPA1 : F1 ,"& "INA9 : H2 ,"& "INA6 : J2 ,"& "EXPA2 : F3 ,"& "INA7 : H3 ,"& "INA4 : K2 ,"& "INA5 : K1 ,"& "INA2 : M1 ,"& "INA0 : N1 ,"& "INA3 : L1 ,"& "IENA : M2 ,"& "INA1 : L2 ,"& "LIB_A : N2 ,"& "LIA_B : N3 ,"& "LIA_A : P2 ,"& "SYNCB : N4 ,"& "SYNCA : P3 ,"& "DTACK : M4 ,"& "SYNCD : N5 ,"& "SYNCC : P4 ,"& "MODE : M5 ,"& "RESET : P5 ,"& "D7 : N6 ,"& "D6 : P6 ,"& "CS : M6 ,"& "D5 : N7 ,"& "D4 : P7 ,"& "D2 : P8 ,"& "R_W : M7 ,"& "D3 : N8 ,"& "D0 : P9 ,"& "TRST : M8 ,"& "D1 : N9 ,"& "SBM0_PA6_LA6 : P10,"& "DS : M9 ,"& "A0 : M11 ,"& "A2 : N10 ,"& --50 "PACH0_LACLKOUT: P11 ,"& "A1 : M10 ,"& "SDIV02_PA7_LA7: P12 ,"& "PACH1_LACLKIN : N11 ,"& "PA4_LA4 : M12 ,"& "SDIV03_PA5_LA5: N12 ,"& "PA3_LA3 : N13 ,"& "PA2_LA2 : M13 ,"& "PA1_LA1 : N14 ,"& "SDIV00_PA8 : L13 ,"& "PA0_LA0 : M14 ,"& "TCLK : L12 ,"& "SDFS0_PA10 : K13 ,"& "SDIV01_PA9 : L14 ,"& "TDO : K12 ,"& "SDO0_PA11 : K14 ,"& "SDFE0_PA12 : J13 ,"& "SCLK1_PA13 : J14 ,"& "SDR0_PAREQ : J12 ,"& "PA14 : H13 ,"& "TMS : G14 ,"& "TDI : G13 ,"& "CHIP_ID1 : F14 ,"& "CHIP_ID0 : F13 ,"& "CHIP_ID3 : E14 ,"& "SDR1_PAACK : D12 ,"& "CHIP_ID2 : E13 ,"& "SDIN1_PAIQ : D14 ,"& "SCLK0 : E12 ,"& "PB6_LB6 : C14 ,"& "SDIN0 : D13 ,"& "PBIQ : C12 ,"& "SDIN2_PB7_LB7 : B14 ,"& "SDFE1_PCLK : C13 ,"& "PBCH0_LBCLKOUT: B13 ,"& "SCLK2_PB3_LB3 : B12 ,"& "PBCH1_LBCLKIN : A13 ,"& "PB0_LB0 : B11 ,"& "PB5_LB5 : A12 ,"& "PB4_LB4 : B10 ,"& "SDFS1_PB2_LB2 : A11 ,"& "SDO1_PA15 : H14 ,"& "SDO2_PB8 : C10 ,"& "SDFS2_PB1_LB1 : A10 ,"& "SDFE2_PB11 : B9 ,"& "SCLK3_PB10 : A9 ,"& "PB9 : C9 ,"& "SDFE3_PB13 : B8 ,"& "SDFS3_PB12 : A8 ,"& "SDO3_PB14 : A7 ,"& --100 "SDR2_PBREQ : C8 ,"& "SDIN3_PB15 : B7 ,"& "INB13 : C4 ,"& "SDR3_PBACK : C7 ,"& "INB12 : B5 ,"& "INB11 : A4 ,"& "PL_SER : A6 ,"& -- should always be tied to VDDIO "EXPB1 : A5 ,"& "INB10 : C5 ,"& "INB9 : A3 ,"& "EXPB0 : B6 ,"& "INB7 : C3 ,"& "INB8 : B4 ,"& "EXPB2 : C6 ,"& "INB5 : B3 ,"& "INB6 : A2 ,"& "INB4 : B2 ,"& "VDDRING : (E5, E7, E9, F10, G5, H10, J5, K6, K8, K10)," & "VSSRING : (H6, H7, H8, H9, J6, J7, J8, J9)," & "VDDCORE:(E6, E8, E10, F5, G10, H5, J10, K5, K7, K9)," & "VSSCORE:(F6, F7, F8, F9, G6, G7, G8, G9)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of TCLK : signal is (1.000000e+07, BOTH); attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of ad6634: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of ad6634: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "HIGHZ (011)," & "CLAMP (100)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of ad6634: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of ad6634: entity is "0000" & -- 4-bit version number "0010011110100011" & -- 16-bit part number 27A3 "00011100101" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of ad6634: entity is "BYPASS (BYPASS, HIGHZ, CLAMP)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of ad6634: entity is 160; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of ad6634: entity is -- -- num cell port function safe [ccell disval rslt] -- "159 (BC_4, SCLK2_PB3_LB3, observe_only, X), " & "158 (BC_1, SCLK2_PB3_LB3, output3, X, 157, 1, PULL0)," & "157 (BC_1, *, control, 1), " & "156 (BC_4, PBCH1_LBCLKIN, observe_only, X), " & "155 (BC_1, PBCH1_LBCLKIN, output3, X, 129, 1, PULL0)," & "154 (BC_1, PB0_LB0, output2, X), " & "153 (BC_1, PB5_LB5, output2, X), " & "152 (BC_1, PB4_LB4, output2, X), " & "151 (BC_4, SDFS1_PB2_LB2, observe_only, X), " & "150 (BC_1, SDFS1_PB2_LB2, output3, X, 149, 1, PULL0)," & "149 (BC_1, *, control, 1), " & "148 (BC_1, SDO2_PB8, output3, X, 147, 1, PULL0)," & "147 (BC_1, *, control, 1), " & "146 (BC_4, SDFS2_PB1_LB1, observe_only, X), " & "145 (BC_1, SDFS2_PB1_LB1, output3, X, 144, 1, PULL0)," & "144 (BC_1, *, control, 1), " & "143 (BC_1, SDFE2_PB11, output2, X), " & "142 (BC_4, SCLK3_PB10, observe_only, X), " & "141 (BC_1, SCLK3_PB10, output3, X, 140, 1, PULL0)," & "140 (BC_1, *, control, 1), " & "139 (BC_1, PB9, output2, X), " & "138 (BC_1, SDFE3_PB13, output2, X), " & "137 (BC_4, SDFS3_PB12, observe_only, X), " & "136 (BC_1, SDFS3_PB12, output3, X, 135, 1, PULL0)," & "135 (BC_1, *, control, 1), " & "134 (BC_1, SDO3_PB14, output3, X, 133, 1, PULL0)," & "133 (BC_1, *, control, 1), " & "132 (BC_1, SDR2_PBREQ, output2, X), " & "131 (BC_4, SDIN3_PB15, observe_only, X), " & "130 (BC_1, SDIN3_PB15, output3, X, 129, 1, PULL0)," & "129 (BC_1, *, control, 1), " & "128 (BC_4, INB13, observe_only, X), " & "127 (BC_4, SDR3_PBACK, observe_only, X), " & "126 (BC_1, *, internal, X), " & "125 (BC_4, INB12, observe_only, X), " & "124 (BC_4, INB11, observe_only, X), " & "123 (BC_4, PL_SER, observe_only, X), " & "122 (BC_4, EXPB1, observe_only, X), " & "121 (BC_4, INB10, observe_only, X), " & "120 (BC_4, INB9, observe_only, X), " & "119 (BC_4, EXPB0, observe_only, X), " & "118 (BC_4, INB7, observe_only, X), " & "117 (BC_4, INB8, observe_only, X), " & "116 (BC_4, EXPB2, observe_only, X), " & "115 (BC_4, INB5, observe_only, X), " & "114 (BC_4, INB6, observe_only, X), " & "113 (BC_4, INB4, observe_only, X), " & "112 (BC_4, INB2, observe_only, X), " & "111 (BC_4, INB3, observe_only, X), " & "110 (BC_4, INB0, observe_only, X), " & "109 (BC_4, INB1, observe_only, X), " & "108 (BC_4, IENB, observe_only, X), " & "107 (BC_1, LIB_B, output2, X), " & "106 (BC_4, CLK, observe_only, X), " & "105 (BC_4, INA13, observe_only, X), " & "104 (BC_4, INA12, observe_only, X), " & "103 (BC_4, EXPA0, observe_only, X), " & "102 (BC_4, INA11, observe_only, X), " & "101 (BC_4, INA10, observe_only, X), " & "100 (BC_4, INA8, observe_only, X), " & "99 (BC_4, EXPA1, observe_only, X), " & "98 (BC_4, INA9, observe_only, X), " & "97 (BC_4, INA6, observe_only, X), " & "96 (BC_4, EXPA2, observe_only, X), " & "95 (BC_4, INA7, observe_only, X), " & "94 (BC_4, INA4, observe_only, X), " & "93 (BC_4, INA5, observe_only, X), " & "92 (BC_4, INA2, observe_only, X), " & "91 (BC_4, INA0, observe_only, X), " & "90 (BC_4, INA3, observe_only, X), " & "89 (BC_4, IENA, observe_only, X), " & "88 (BC_4, INA1, observe_only, X), " & "87 (BC_1, LIB_A, output2, X), " & "86 (BC_1, LIA_B, output2, X), " & "85 (BC_1, LIA_A, output2, X), " & "84 (BC_4, SYNCB, observe_only, X), " & "83 (BC_4, SYNCA, observe_only, X), " & "82 (BC_1, DTACK, output2, X), " & "81 (BC_4, SYNCD, observe_only, X), " & "80 (BC_4, SYNCC, observe_only, X), " & "79 (BC_4, MODE, observe_only, X), " & "78 (BC_4, RESET, observe_only, X), " & "77 (BC_4, D7, observe_only, X), " & "76 (BC_1, D7, output3, X, 59, 1, PULL0)," & "75 (BC_4, D6, observe_only, X), " & "74 (BC_1, D6, output3, X, 59, 1, PULL0)," & "73 (BC_4, CS, observe_only, X), " & "72 (BC_4, D5, observe_only, X), " & "71 (BC_1, D5, output3, X, 59, 1, PULL0)," & "70 (BC_4, D4, observe_only, X), " & "69 (BC_1, D4, output3, X, 59, 1, PULL0)," & "68 (BC_4, D2, observe_only, X), " & "67 (BC_1, D2, output3, X, 59, 1, PULL0)," & "66 (BC_4, R_W, observe_only, X), " & "65 (BC_4, D3, observe_only, X), " & "64 (BC_1, D3, output3, X, 59, 1, PULL0)," & "63 (BC_4, D0, observe_only, X), " & "62 (BC_1, D0, output3, X, 59, 1, PULL0)," & "61 (BC_4, D1, observe_only, X), " & "60 (BC_1, D1, output3, X, 59, 1, PULL0)," & "59 (BC_1, *, control, 1), " & "58 (BC_4, SBM0_PA6_LA6, observe_only, X), " & "57 (BC_1, SBM0_PA6_LA6, output3, X, 43, 1, PULL0)," & "56 (BC_4, DS, observe_only, x), " & "55 (BC_4, A0, observe_only, x), " & "54 (BC_4, A2, observe_only, x), " & "53 (BC_1, PACH0_LACLKOUT, output2, X), " & "52 (BC_4, A1, observe_only, x), " & "51 (BC_4, SDIV02_PA7_LA7, observe_only, X), " & "50 (BC_1, SDIV02_PA7_LA7, output3, X, 43, 1, PULL0)," & "49 (BC_4, PACH1_LACLKIN, observe_only, X), " & "48 (BC_1, PACH1_LACLKIN, output3, X, 43, 1, PULL0)," & "47 (BC_1, PA4_LA4, output2, X), " & "46 (BC_4, SDIV03_PA5_LA5, observe_only, X), " & "45 (BC_1, SDIV03_PA5_LA5, output3, X, 43, 1, PULL0)," & "44 (BC_1, PA3_LA3, output2, X), " & "43 (BC_1, *, control, 1), " & "42 (BC_1, PA2_LA2, output2, X), " & "41 (BC_1, PA1_LA1, output2, X), " & "40 (BC_4, SDIV00_PA8, observe_only, X), " & "39 (BC_1, SDIV00_PA8, output3, X, 2, 1, PULL0)," & "38 (BC_1, PA0_LA0, output2, X), " & "37 (BC_4, SDFS0_PA10, observe_only, X), " & "36 (BC_1, SDFS0_PA10, output3, X, 35, 1, PULL0)," & "35 (BC_1, *, control, 1), " & "34 (BC_4, SDIV01_PA9, observe_only, X), " & "33 (BC_1, SDIV01_PA9, output3, X, 2, 1, PULL0)," & "32 (BC_1, SDO0_PA11, output3, X, 31, 1, PULL0)," & "31 (BC_1, *, control, 1), " & "30 (BC_1, SDFE0_PA12, output2, X), " & "29 (BC_4, SCLK1_PA13, observe_only, X), " & "28 (BC_1, SCLK1_PA13, output3, X, 27, 1, PULL0)," & "27 (BC_1, *, control, 1), " & "26 (BC_1, SDR0_PAREQ, output2, X), " & "25 (BC_1, PA14, output2, X), " & "24 (BC_1, SDO1_PA15, output3, X, 23, 1, PULL0)," & "23 (BC_1, *, control, 1), " & "22 (BC_4, CHIP_ID1, observe_only, X), " & "21 (BC_4, CHIP_ID0, observe_only, X), " & "20 (BC_4, CHIP_ID3, observe_only, X), " & "19 (BC_4, SDR1_PAACK, observe_only, X), " & "18 (BC_1, *, internal, X), " & "17 (BC_4, CHIP_ID2, observe_only, X), " & "16 (BC_4, SDIN1_PAIQ, observe_only, X), " & "15 (BC_1, SDIN1_PAIQ, output3, X, 2 , 1, PULL0)," & "14 (BC_4, SCLK0, observe_only, X), " & "13 (BC_1, SCLK0, output3, X, 12 , 1, PULL0)," & "12 (BC_1, *, control, 1), " & "11 (BC_1, PB6_LB6, output2, X), " & "10 (BC_4, SDIN0, observe_only, X), " & "9 (BC_1, PBIQ, output2, X), " & "8 (BC_4, SDIN2_PB7_LB7, observe_only, X), " & "7 (BC_1, SDIN2_PB7_LB7, output3, X, 1 , 1, PULL0)," & "6 (BC_4, SDFE1_PCLK, observe_only, X), " & "5 (BC_1, SDFE1_PCLK, output3, x, 4 , 1, PULL0)," & "4 (BC_1, *, control, 1), " & "3 (BC_1, PBCH0_LBCLKOUT, output2, x), " & "2 (BC_1, *, control, 1), " & "1 (BC_1, *, control, 1), " & "0 (BC_1, *, internal, 1)"; end ad6634;